In recent years, smart power technologies have gained more importance. Smart power technologies offer the integration of analog and digital circuit (e.g., bipolar and CMOS devices) combined with the power stage (e.g., DMOS devices) on a single chip. As such, smart power technologies provide more features to choose among high density lower power consumption of CMOS, high power drive capability and high speed of bipolar, and large current and high breakdown voltage of DMOS. The combination of multiple functions (including analog, digital and power) on a single chip enables miniature system design for different applications in the fields of automotive, industrial, telecommunication and electronic data process. In addition, smart power technologies include diagnostic and protection functions to the power transistors, which increase the robustness and reliability of power driver for various applications.
Today's smart power applications require gate drivers to drive power transistors (such as MOSFET or IGBT) in the range of 50-1200V. The key issue for high voltage is the design of the power device and the process of integrating it with low voltage devices. FIG. 1A is a top view of a conventional high voltage gate driver integrated circuit and FIG. 1B is a cross-sectional view of the conventional high voltage gate driver integrated circuit of FIG. 1A. Referring to FIGS. 1A and 1B, a high voltage gate driver integrated circuit 10 typically includes a low voltage circuit region 12 and a high voltage circuit region 14 inside a high voltage floating tub. In the present description, the term “high voltage circuit region” refers to a circuit region of low voltage circuits that are sitting inside a high voltage floating tub that encompasses the high voltage circuit region 14. The floating tub includes a RESURF region 11 that terminates a high voltage circuit region. A resistor inside the high voltage floating tub determines the voltage that triggers the control circuitry that turns on the high side power transistor. A junction termination region 16 is disposed between the low voltage region 12 and the high voltage floating tub 11. The junction termination region 16 provides an electrical isolation between the low voltage circuit region 12 and the high voltage circuit region 14. A level shifter 18, such as one or more N-type lateral double-diffused MOS (LDMOS) transistors, are disposed in the low voltage region 12 for level-shifting a signal voltage referenced to ground to a signal voltage referenced to the high voltage floating tub. The level shifter 18 is formed inside an N-buried layer and grounded to the p-type substrate. The level shifter 18 may be a lateral LDMOS made using a N− drain region. A source of the LDMOS can be isolated inside the N-drain region or may sit directly in P-type substrate.
The level shifter 18 and the high voltage circuit region 14 are electrically connected by metal 13. The metal 13 connects the drain of the level shifter 18 and crosses the junction isolation 16 to connect to the high voltage circuitry in the high voltage circuit region 14. Since the metal 13 is connected to high voltage (such as 600V), this can cause high electric field in silicon under the metal 13 and causing snapback and breakdown degradation. Alternatively, the level-shifting device (LDMOS) may be merged into the high voltage circuit region to avoid breakdown degradation due to metal crossing. However, the leakage current between LDMOS drain and high voltage circuit region becomes an issue. The high voltage gate driver integrated circuit 10 also employs N-type buried layer structure 19 formed between the P-type substrate 17 and the N-type epitaxial layer 20. The N-type buried layer 19 (NBL) is formed in both the high voltage circuit region 14 and the low voltage circuit region 12 to reduce parasitic PNP conduction and prevent latch-up. Buried layers require additional processing steps in the fabrication of the high voltage gate driver integrated circuit and thus increase the cost of manufacturing.
FIG. 2A is a cross-sectional view of a conventional high voltage gate driver integrated circuit built using P-epi with lower spacing between high side tub and the substrate pick-up. FIG. 2B is a cross-sectional view of a conventional high voltage gate driver integrated circuit with an adjacent low voltage N-tub next to a high voltage N-tub. However, the depletion (as shown in dashed lines in FIGS. 2A and 2B) is under the high voltage interconnect and it causes high electric field in silicon under the interconnect. Also, the depletion curves and spreads under the p-well region causing PNP punch through in the situation depicted in FIG. 2B. In the situation shown in FIG. 2A, the depletion curvature results in high electric field, which causes snap-back.
It is within this context that embodiments of the present invention arise